Power sequences Variation

Power sequences Variation

The Sequencer is one of many blocks designed to fit complex wiring into a single block. knowing as a geometric sequence, is a set of values with a constant multiplier to go from one value to the next . Analog Devices provides a broad portfolio of sequencing and monitoring solutions, offering both analog and digitally programmable power supply sequencers to solve designers’ power supply requirements. Sequences diagram is a simple power system requirements, while digitally programmable sequencers provide a large number of power supply

inputs for monitoring and sequencing with in-circuit . 

Starting on step -7 adaptor voltage flow to charger ic and if no interupted on current detector ,charger ic will let adp+ current trough battery fet and stanby sources for n channel discrete for smps pwr_suply on -6 step and produce 5V_auxilary power on -5step .after that 3D3V_auxilari power the Embedded controler KBC on step -4 ,than kbc giving enable signal for Smps pwr_supply to activated 3V and 5V system on step -3 and than ready to supply all voltage rail including Bios power ,if all this requirment available bios and EC active will sent PM_RSMRST signal ..this minus step call VALW or power always before switching..........
Power on switch started when power button pressed on step 1 by sending switching signal to EC and than EC sending PWRBTN MCP to swicth on MCP51 South bridge on step 2 than MCP51 will sending PM_SLP_S5 to enable TPS5116 on step 3 than activated CPUmemory and Sodim VCCRAM power supply on step 4...TPS 5116 also supply 1D8V MCP51 on step 5 than MCP52 sending PM_SLP_S3 to enable MAX 8783 to enable 1D2V for MCP51 southbridge and C51M Northbridge VS power on step 6 and 7...than MCP51 giving enable signal to Max8760 to activated VCCORE Processor power on step 8,activated VCCORE pwr supply on step 9 also sending VRM PWRGD to MCP51 on step 10...than MCP51 sending enable signal for 1D2V_HT on gate N channel AO3400 on step 11 and supply to C51M and CPU on step 12..after that C51M sending 1D2V_HT to MCP51 on step 13.

After Charger ic passing adp+ voltage and SMPS produced 3V and 5V power sources Reset IC will powering Embedded controler on step 2 than EC sending VSUS enable signal on step 3 than SUS PWRSG sending back to EC on step 4 EC is actived and sending PM_RSMRST to ICH 8 on step 5 than power button presset sending switching signal to EC on step 7 than EC switch on ICH8 by sending PM_PWRBTN at step 7 to power on ICH 8 and sending SLP_s3 and SLP_S4 to EC and activate power management and activated SUSC_ON on step 7 and activated SUSB_ON on step 9 and sending all system powergood back to EC than EC enable Vccore IC enable signal (CPU_VRON) to powered processor on step 11 than CPU active than sending CPU_PWRGD to EC on step 12 than EC sent PM_PWRGD to ICH8 on step 13 and ICH 8 sending CLK_PWRGD to activated clock generator on step 14 than sending GMCH 965PM PM+PWRGD on step 15....than ICH8 sending H_PWRGD to CPU and also sending PLT_RST signal to 965PM on step 16 on same time.than 965PM sending H_CPURST to activated CPU on step 17.

some of circuit using Fuses to protect the circuit ,check fuse location code on schema and it will identified by standard code .Than make sure ADP+ flow to the Voltage Rail requerment for .you can check measuring point for ADP+,5V and 3V needs to power on the Circuit .