SOUTHBRIDGE AND Northbridge

The Southbridge is an integrated circuit on the motherboard that is responsible for the hard drive controller, I/O controller and integrated hardware such as sound card, video card if present on the motherboard, USB, PCI, ISA, IDE, BIOS, and Ethernet. The southbridge gets its name for commonly being South of the PCI bus. The southbridge is one of the two chips in the core logic chipset on a personal computer (PC) motherboard, the other being the northbridge. The southbridge typically implements the slower capabilities of the motherboard in a northbridge/southbridge chipset computer architecture

Hand shake between CPU-SB and clock generator

SB Power Button Timing

S1 and S2 Reset Timing

The SB controls the system reset signal timings, which are provided in this section.
ROMRST#
ROMRST# is used for resetting the LPC system ROM. The SB generates ROMRST# and controls the required timing for this signal. Depending on the system configuration, the timing of ROMRST# may be referenced to RSMRST# or A_RST#. Enabling the Embedded Controller (EC) will force the SB to deassert ROMRST# with respect to RSMRST#. This allows the EC to access the ROM before the system access cycle begins.
The ROMRST# timing is shown with respect to RSMRST# and A_RST# 
indicates the timing value that are applicable to each platform configuration.

S3 Timing

S3_S5 runing on EC after SUSB and SUSC sent back to EC

S4 and S5 Timing

Hand shake between Clk_Gen with CPU and ICH

Operates at a very small current. Care must be taken when working with this circuit.
To ensure the accuracy of the ICH/PCH RTC circuit for each specific board design and
RTC circuit layout, the external load capacitance should be optimized by choosing
correct values of the tuning fork capacitors C1/C2.
The occurrence of time-loss under environmental stress conditions is dependent on
motherboard factors (cleanliness, discrete component characteristics, layout, fork
capacitor values), and condensation. If time-loss is observed on your system, check all
of the sources of inaccuracy listed in this document to improve immunity of the internal
ICH/PCH oscillator to time loss.

intel HM 65 Soutbridge 

intel CG82 NM 10 Southbridge 

intel 8201 HBM Southbridge

AMD SB-820 Southbridge